1. Field of the Invention
The present invention relates to a circuit arrangement which changes a pulse-density-modulated signal ("PDM signal") into an analog signal corresponding to the time average of the PDM signal, thus, representing a digital-to-analog ("D/A") conversion of the PDM signal, depending on the degree of smoothing. Such circuit arrangements are used mainly in pulse-density analog-to-digital ("A/D") converters having sigma-delta modulators in their feedback paths.
2. Description of the Related Art
U.S. Pat. No. 4,156,871, for example, shows in FIG. 1 the circuit of a pulse-density A/D converter whose output, namely the PDM signal, is fed back through an averaging RC low-pass filter The capacitor of the RC low-pass filter is connected through a resistor to the input for the analog signal to be converted.
In "Analog/Digital-Umsetzung mit einem Pulsdichtemodulator," ("Analog/Digital-Conversion with a Pulse-density Modulator"), Elektronik, No. 19, Sept. 20, 1985, pp. 75 to 77, by Heinrich Pfeifer, further examples of pulse-density A/D or D/A converters are shown which contain sigma-delta modulators and at least one PDM-signal-averaging device including an RC low-pass filter or an integrator. In the Heinrich article, it is stated that the conversion of pulse-code-modulated signals ("PCM signals") into PDM signals by means of a digital pulse-density modulator is simple, and that, on the other hand, it is also readily possible to derive from the PDM signal a PCM signal with a lower sampling rate and a greater number of bits by means of a decimation filter (i.e., a digital low-pass filter), so that, via this PDM intermediate phase, an advantageous high-resolution D/A or A/D conversion is obtained for ordinary PCM signals. For an audio-signal bandwidth of 15 KHz and at a clock frequency of 4.5 MHz, for example, a theoretical signal-to-noise ratio of 85 dB is obtained, so that the maximum possible resolution is about 14 bits in the case of a binary number code.
The attainable resolution of the PDM signals during A/D and D/A conversion depends on the accuracy of the averaging. A particularly disturbing source of error is clock-signal jitter, which causes PDM-signal-edge jitter, which produces a noise signal superposed on the average value.
Auslegeschrift 27 17 042 (corresponding to U.S. Pat. No. 4,125,803) describes the use of a shift register in a D/A converter wherein the shift register is part of a current distribution circuit. The current distribution circuit provides a number of direct-current pairs which have highly accurate magnitude ratios that can be expressed in integers. By means of a switch arrangement controlled by the parallel output of the shift register, a first number and a second number of currents of the same magnitude are switched to a first summing point and a second summing point, respectively, with the shift register switching the individual currents at regular intervals in such a manner that during one cycle, all existing currents contribute to the summation the same number of times, and thus for the same period.
Since all currents are derived from a single current source by division, the deviations of the individual currents compensate each other in each complete cycle, which covers n clock periods During the cycle, the shift register is connected as a ring. The shift signal must be free of jitter. The circuit arrangement of Auslegeschrift 27 17 042 thus differs considerably from the subject matter of the present invention, as will be described below.